SCEC 2017

Software Challenges to Exascale Computing

First Workshop on Software Challenges to Exascale Computing
December 17, 2017
9:00 AM - 7:00 PM


Supercomputing or High Performance Computing (HPC) platforms are used to power discoveries and to reduce the time-to-results in a wide variety of disciplines (such as, astrophysics, archaeology, and financial trading). For optimally utilizing these high-end platforms, it is critical to have scalable and efficient software (applications, middleware, libraries, and tools) that can take advantage of the innovative hardware features in these platforms. However, developing and maintaining HPC software remains a challenging task because the HPC platforms for which they are developed typically have a short life-span, and are replaced with next generation platforms within a few years. As we progress towards the exascale computing era, the task of developing and maintaining HPC software is likely to become even more challenging than now due to the increasing complexity of the HPC platforms and the pressing need for power-efficiency and memory usage optimization. There is a potential of mitigating some of the challenges related to developing HPC software for the current and future generation systems by adopting the innovations in the advanced software engineering sub-disciplines, such as model-driven engineering, generative programming, and adaptive and reflective software systems.

The goals of the first workshop on "Software Challenges to Exascale Computing" are to foster international collaborations across the HPC and the advanced software engineering disciplines, and to exchange knowledge on the challenges and solution strategies for developing scalable and efficient HPC software. The workshop attendees will learn about the state-of-the-art and the state-of-the-practice in the areas of HPC software development and advanced software engineering through presentations, hands-on sessions, and open-discussion sessions. Those already skilled in the advanced software engineering discipline will learn about the challenges and opportunities in the HPC domain, and can find interesting test cases for generalizing their innovative approaches.

The workshop will provide a forum through which hardware vendors and software developers can communicate with each other and influence the architecture of the next generation supercomputing systems and the supporting software stack. By fostering cross-disciplinary associations, the workshop will serve as a stepping stone towards innovations in the future.


Benefits to the researchers and users in the academia: disseminate your results to the public, and find potential collaborators.

Benefits to software developers: understand the future trends in the HPC hardware and develop collaborations in the code modernization and optimization disciplines.

Benefits to HPC service providers: understand the challenges that the community faces in using the HPC platforms efficiently, and connect with the user-community.

Benefits to HPC hardware vendors: understand the evolving needs of the HPC community, and network with potential customers.

Benefits to students: network with HPC and advanced software engineering professionals and researchers, learn about internship and career opportunities, discuss the opportunities for higher education.

Workshop Topics

Best practices for HPC software development
Software tools for HPC code modernization and optimization
Supporting software and middleware for HPC environments
High-level interfaces, libraries, compilers, and runtime systems for parallel programming
Innovations in efficient utilization of memory hierarchies on HPC platforms
Techniques for developing power-efficient applications
Software support for HPC in the cloud
Application of generative programming and model-driven engineering techniques for solving large-scale problems
Design and development of adaptive and reflective systems

Tentative Agenda

Time Topic Speaker
09:00-09:30 Registration, badges, kit-bag pick-up Location TBD
09:30-10:00 Welcome to the workshop - overview & goals Ritu Arora, TACC/ Sharda Dixit, C-DAC
Welcome from C-DAC Hemant Darbari, C-DAC
10:00-10:30 Advanced Cyberinfrastructure in Science and Engineering Vipin Chaudhary, NSF
Abstract: Advanced cyberinfrastructure and the ability to perform large-scale simulations and accumulate massive amounts of data have revolutionized scientific and engineering disciplines. In this talk I will give an overview of the National Strategic Computing Initiative (NSCI) that was launched by Executive Order (EO) 13702 in July 2015 to advance U.S. leadership in high performance computing (HPC). The NSCI is a whole-of-nation effort designed to create a cohesive, multi-agency strategic vision and Federal investment strategy, executed in collaboration with industry and academia, to maximize the benefits of HPC for the United States. I will then discuss NSF's role in NSCI and present three cross-cutting software programs ranging from extreme scale parallelism to supporting robust, reliable and sustainable software that will support and advance sustained scientific innovation and discovery.
Bio: A veteran of High Performance Computing (HPC), Dr. Chaudhary has been actively participating in the science, business, government, and technology innovation frontiers of HPC for over two decades. His contributions range from heading research laboratories and holding executive management positions, to starting new technology ventures. He is currently a Program Director in the Office of Advanced Cyberinfrastructure at National Science Foundation. He is Empire Innovation Professor of Computer Science and Engineering at the Center for Computational Research at the New York State Center of Excellence in Bioinformatics and Life Sciences at SUNY Buffalo, and the Director of the university's Data Intensive Computing Initiative. He is also the co-founder of the Center for Computational and Data-Enabled Science and Engineering.
He cofounded Scalable Informatics, a leading provider of pragmatic, high performance software-defined storage and compute solutions to a wide range of markets, from financial and scientific computing to research and big data analytics. From 2010 to 2013, Dr. Chaudhary was the Chief Executive Officer of Computational Research Laboratories (CRL) where he grew the company globally to be an HPC cloud and solutions leader before selling it to Tata Consulting Services. Prior to this, as Senior Director of Advanced Development at Cradle Technologies, Inc., he was responsible for advanced programming tools for multi-processor chips. He was also the Chief Architect at Corio Inc., which had a successful IPO in June, 2000.
Dr. Chaudhary's research interests are in High Performance Computing and Applications to Science, Engineering, Biology, and Medicine; Big Data; Computer Assisted Diagnosis and Interventions; Medical Image Processing; Computer Architecture and Embedded Systems; and Spectrum Management. He has published approximately 200 papers in peer-reviewed journals and conferences and has been the principal or co-principal investigator on over $28 million in research projects from government agencies and industry. Dr. Chaudhary was awarded the prestigious President of India Gold Medal in 1986 for securing the first rank amongst graduating students at the Indian Institute of Technology (IIT). He received the B.Tech. (Hons.) degree in Computer Science and Engineering from the Indian Institute of Technology, Kharagpur, in 1986 and a Ph.D. degree from The University of Texas at Austin in 1992.
10:30-11:00 A User-Defined Code Transformation Approach to Separation of Performance Concerns Hiroyuki Takizawa,
Tohoku University
Abstract: Today, high-performance computing (HPC) application codes are often optimized and specialized for a particular system configuration to exploit the system's potential. One severe problem is that simply modifying an HPC application code often results in degrading the performance portability, readability, and maintainability of the code. Therefore, we have been developing a code transformation framework, Xevolver, so that users can easily define their own code transformation rules for individual cases, in order to express how each application code should be changed to achieve high performance. In this talk, I will briefly review the Xevolver framework and introduce some case studies to discuss the benefits of the user-defined code transformation approach.
Bio: Hiroyuki Takizawa is currently a professor of Cyberscience Center, Tohoku University. His research interests include performance-aware programming, high-performance computing systems and their applications. Since 2011, he is leading a research project, supported by JST CREST, to explore an effective way of assisting legacy HPC code migration to future-generation extreme-scale computing systems. He received the B.E. Degree in Mechanical Engineering, and the M.S. and Ph.D. Degrees in Information Sciences from Tohoku University in 1995, 1997 and 1999, respectively.
11:00-11:15 Coffee Break & Networking
11:15-11:45 Technologies for Exascale Computing Nash Palaniswamy,
Abstract: Intel is investing in a broad set of technologies to move computing to the address the challenges of Exascale computing. These technologies are targeted to reach next generation performance in a configurable system that can achieve exceptional performance in data analytics, traditional high performance computing and artificial intelligence. Being able to address all of these application domains is of critical importance.
Intel is investing in processors, fabric, memory and software. Each will be discussed along with their respective importance in achieving Exascale.
Bio: Dr. Nash Palaniswamy has been at Intel since October 2005, and focuses in the area of Enterprise and High Performance Computing in the Datacenter group. He is currently the Senior Director for Worldwide Solutions Enablement and Revenue Management for Enterprise and HPC. In this role, he is responsible for managing all strategic opportunities in Enterprise and HPC and managing and meeting revenue for the Enterprise and Government segment in Intel's datacenter group. Dr. Palaniswamy leads a team that drives strategic opportunities worldwide (solutions, architecture, products, business frameworks, etc) in collaboration with Intel's ecosystem partners.
His prior responsibilities at Intel included being the lead for worldwide business development and operations for Intel® Technical Computing Solutions, Intel® QuickAssist Technology based accelerators in HPC, and World Wide Web Consortium Advisory Committee representative from Intel. Prior to joining Intel as part of the acquisition of Conformative Systems, an XML Accelerator Company, he has served in several senior executive positions in the industry including being the Director of System Architecture at Conformative Systems, CTO/VP of Engineering at MSU Devices (a publicly traded company), and Director of Java Program Office and Wireless Software Strategy in the Digital Experience Group of Motorola, Inc.
Dr. Palaniswamy holds a B.S. in Electronics and Communications Engineering from Anna University (Chennai, India) and an M.S. and Ph.D. from the University of Cincinnati in Electrical and Computer Engineering.
11:45-12:15 Overcoming Deployment and Configuration Challenges in High Performance Computing via Model-driven Engineering Technologies Aniruddha Gokhale,
Vanderbilt University
Abstract: As systems scale in size and complexity, reasoning about their properties and controlling their behavior requires complex simulations, which often involves multiple interacting co-simulators that must be deployed and configured on high performance computing resources. Increasingly, cloud platforms which may even be federated, offer cost-effective solutions to realize such deployments. However, researchers and practitioners alike often face a plethora of challenges stemming from the need for rapid provisioning/deprovisioning, ensuring reliability, defining strategies for autoscaling against changing workloads, handling resource unavailabilities, and exploiting modern features such as GPUs, FPGAs, and NUMA architectures to name a few, for which they generally tend to lack the expertise to overcome these challenges. Model-driven engineering (MDE) offers significant promise to address these challenges by providing the users with intuitive abstractions and automating the deployment and configuration tasks. This talk describes our ongoing work in this space and will highlight both the MDE and systems solutions that we are investigating.
Bio: Dr. Aniruddha S. Gokhale is an Associate Professor in the Department of Electrical Engineering and Computer Science, and Senior Research Scientist at the Institute for Software Integrated Systems (ISIS) both at Vanderbilt University, Nashville, TN, USA. His current research focuses on developing novel solutions to emerging challenges in edge-to-cloud computing, real-time stream processing, and publish/subscribe systems as applied to cyber physical systems including smart transportation and smart cities. He is also working on using cloud computing technologies for STEM education. Dr. Gokhale obtained his B.E (Computer Engineering) from University of Pune, India, 1989; MS (Computer Science) from Arizona State University, 1992; and D.Sc (Computer Science) from Washington University in St. Louis, 1998. Prior to joining Vanderbilt, Dr. Gokhale was a member of technical staff at Lucent Bell Laboratories, NJ. Dr. Gokhale is a Senior member of both IEEE and ACM, and a member of ASEE. His research has been funded over the years by DARPA, DoD, industry and NSF including a NSF CAREER award in 2009.
12:15-12:45 The EX Factor in the Exascale Era: Factors driving changes in HPC Bharatkumar Sharma,
Abstract: GPU's has been used to accelerate HPC algorithms which are based on first principles theory and are proven statistical models for accurate results in multiple science domains. This talk will provide insights into the HPC domain and how it affects the programs you write today and in the future in various domains.
Bio: Bharatkumar Sharma obtained master degree in Information Technology from Indian Institute of Information Technology, Bangalore. He has around 10 years of development and research experience in domain of Software Architecture, Distributed and Parallel Computing. He is currently working with Nvidia as a Senior Solution Architect, South Asia. He has published papers and journal articles in field of Parallel Computing and Software Architecture.
12:45-13:15 Lunch Break & Networking
13:45-15:10 Lighting Talks TBD
Neethi Suresh, Lois Thomas and Bipin Kumar, "DNS for large domains: Challenges for computation and storage"

Manu Awasthi, "DRAM Organization Aware OS Page Allocation"

Gouri Kadam and Shweta Nayak, "Implementation of OpenSource Structural Engineering Application OpenSees on GPU platform"

Mangala N, Shamjith K V, Deepika H.V and Prachi Pandey, "Adaptive Resource Allocation Technique for Exascale Systems"

Shreya Bokare, Sanjay Pawar and Veena Tyagi."Network coded Storage I/O subsystem for HPC exascale applications"

Manavalan R."Application level challenges and issues of processing different frequency, polarization and incidence angle Synthetic Aperture Radar data using distributed computing resources"

Venkatesh Shenoi, Janakiraman S and Sandeep Joshi, "Towards energy efficient numerical weather prediction Scalable algorithms and approaches"
14:50-15:10 "MPPLAB(E-Teacher)" Ritu Arora, TACC
15:10-15:30 Coffee Break & Networking
15:30-17:00 Hands-on session: Using the Interactive Parallelization Tool (IPT) to Generate OpenMP, MPI, and CUDA Programs Ritu Arora, TACC
17:00-17:30 Parallel programming contest (MPI/OpenMP/CUDA) - parallelize programs with or without IPT - C/C++ as the base language - prizes for top contestants - The winner award is Nvidia Tesla K40C GPU
17:30-18:00 Panel Discussion
17:30-18:00 Networking Reception and Prize Winner Announced

Important Dates

Registration opens on: November 1, 2017
Abstract Submission Deadline: November 15, 2017 (original),
November 20, 2017 (extended)
Acceptance Notification: November 25, 2017
Registration with fee waiver closes on: December 7, 2017
Final submission deadline: December 7, 2017
Workshop will be held on: December 17, 2017

Workshop Chairs

Ritu Arora,Texas Advanced Computing Center, USA
Sharda Dixit, Centre for Development of Advanced Computing, India

Nitin Sukhija, Slippery Rock University of Pennsylvania, USA V Venkatesh Shenoi, Centre for Development of Advanced Computing, India

Program Committee
Amarjeet Sharma, Centre for Development of Advanced Computing, India

Amit Majumdar, San Diego Supercomputing Center, USA

Anil Kumar Gupta, Centre for Development of Advanced Computing, India

Antonio Iglesias Gomez, Oak Ridge National Laboratory, USA
Carlos Rosales Fernandez, Intel, USA

Lars Koesterke, Texas Advanced Computing Center, USA

Sandeep K Joshi, Centre for Development of Advanced Computing, India

Seetha Ram Krishna Nookala, Intel, India

Shreya Bokare, Centre for Development of Advanced Computing, India

Soham Ghosh, Centre for Development of Advanced Computing, India

Suman Roychoudhury, Tata Consultancy Services, India

VCV Rao, Centre for Development of Advanced Computing, India

Vinodh Kumar M, Centre for Development of Advanced Computing, India

Gerald Joshua, Texas Advanced Computing Center, USA

CFA (Call For Abstracts)

The SCEC workshop will include a track for lightning talks during which ten-minute talks will be presented in a sequence. The talks will provide a high-level overview of the topics that are aligned with the theme of the workshop. While the time allocated for the lightening talks may not be enough for presenting the fine details of the chosen topic, it could be enough for including key information that piques the interest of the audience for an engaging discussion after the talk. The abstract and slides of the talks will be published on the workshop website. There can be multiple authors on a submission but only one presenter is permitted for each lightning talk due to time-constraints.

Guidelines for preparing the submission for the lightning talk are as follows:

In maximum 300 words, the abstract should answer the following questions on a topic that is relevant to the workshop:
  • What is the software challenge/problem that is being solved?
  • Why is this challenge/problem important to the HPC and/or the advanced software engineering community?
  • If applicable, who will benefit from the software/approach?
  • If applicable, what is the novelty of the software/approach?
  • If applicable, how do the preliminary results compare to those of the related work?

A rough draft of the proposed presentation (up to 5 slides) should also be submitted along with the abstract. The abstracts and the slides must be submitted in the PDF format through the submission system at the following URL:

Abstracts will not be accepted over email. Abstracts which are incomplete or received after the deadline will not be considered. The submission system will close on November 20, 2017.

Presentation guidelines:

Lightning talk presentations are limited to one per speaker. Co-authors are not included in this rule. A person can be a co-author on any number of abstracts.


The registration fees for the workshop is Rupees 1000 (US $16) and can be paid at the venue using cash or credit/debit card. With the support of our sponsors, we are able to waive off the fee for a selected number of particpants who are registered by December 7, 2017. For requesting the fee waiver, please send an email at "" with the subject line "Registration Fee Waiver" and let us know how the fee waiver will help you. All the workshop attendees should register in advance by filling the following form:

Workshop Venue

Hotel Royal Orchid
Opposite to BSNL Office, Near Durgapura Flyover, Tonk Road, Durgapura, Jaipur Rajasthan India 302018


For any questions regarding the workshop, please contact us at:

Workshop Presenters

Ritu Arora, Texas Advanced Computing Center

Vipin Chaudhary, NSF

Hiroyuki Takizawa, Tohoku University

Nash Palaniswamy, Intel

Aniruddha Gokhale, Vanderbilt University

Bharatkumar Sharma, Nvidia

Sharda Dixit, C-DAC

Hemant Darbari, C-DAC


Venkatesh Shenoi, C-DAC

Shreya Bokare, C-DAC

Manavalan R, C-DAC

Gouri Kadam, C-DAC

Mangala N, C-DAC

Manu Awasthi, IIT-Gandhinagar

Neethi Suresh, Indian Institute of Tropical Meteorology


Intel logo

Nvidia logo

NSF logo

TACC logo

NSM logo

C-DAC logo