Click here to go to the TACC Home Page Scalability & Performance Optimization Team - SPOT Click here to go to the UT Home Page
Project Abstract:

As HPC systems grow in size and capability, they also continue to grow in complexity, hence creating additional difficulties for code optimization on these systems. The complexity of the processor, cache, and node design, and the growing imbalance between processor peak performance and the latency and bandwidth to local and remote memory, lead to low performance and scalability. There are many performance measurement and optimization tools in development and in use to help with addressing these issues, but these tools are often vendor-specific, possess steep learning curves, and are not sufficiently comprehensive, thus for example requiring the use of separate tools for performance measurement, processor/cache optimization, and communications optimization. This project will build on previous DoD PET projects to optimize strategic DoD HPC applications and also produce detailed case studies on how these codes were profiled, how the tools were used, and what results were accomplished.

TACC Project Lead: Avi Purkayastha
Collaborators:
Chona Guiang, TACC, UT Austin
Jay Boisseau, TACC, UT Austin
Kent Milfeld, TACC, UT Austin
Karl Schulz, TACC, UT Austin
Tommy Minyard, TACC, UT Austin
Patrick Hurley, TACC, UT Austin
Bill Barth, TACC, UT Austin
Supporting Grants:
Programming Environment & Training funded by Department of Defense

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